Application specific integrated circuits (ASICs) have been available for a number of years. A full-custom ASIC is a device which requires all layers in a semiconductor process to be created in a custom fashion. The process of creating a full-custom ASIC is costly, time consuming, and error prone. Throughout the years much effort has been put in to minimizing the drawbacks of full-custom ASICs. The gate array was created for smaller logic designs where the base chip came as an array of standard digital cells (e.g. AND, OR, and NAND gates). The final product was realized by adding the layers required to interconnect these standard cells to realize a particular function. A gate array is considered a semi-custom ASIC. Some time after gate arrays came field programmable gate arrays (FPGAs). As the name implies, the FPGA all but eliminated the custom portion of the design process. By virtue of their field programmability, there is no fabrication in the development process. However, FPGA technology is not able to compete with full-custom ASIC technology on performance and device cost. More recently, the use of gate arrays has increased with the advent of structured array technology which is essentially equivalent to gate arrays, but on a much larger scale. Most structured arrays minimize the number of layers that have to be configured, yet still offer significant performance and device cost advantages when compared to FPGAs.
Thus far, structured array technology has focused on all digital devices. Most structured arrays combine large numbers of logic circuits into a logic cell to create a device that is specifically adapted for a particular application, but at a cost that is lower than that of developing a completely new device from scratch. Like most integrated circuits, structured arrays are manufactured using a lithographic process that depends on having a mask for each layer of the chip. Some masks may be generic, but others are custom. It is the custom masks that impart the application specificity to the chip by programming the logic cells during the manufacturing process. Reducing the number of custom masks to just one mask provides significant cost and time savings. A “one mask” device allows all of the masks to remain generic except for a single mask, thus allowing the semiconductor manufacturer to invest in the generic or base masks just one time. Various designs may be implemented by customizing just a single mask instead of a complete mask set.